The newest accelerators powering the world's AI clusters share an unusual provenance: substantial portions of their floor plans, interconnect layouts and power-delivery networks were designed by the previous generation of the same class of models they exist to run. Chip architects describe the loop plainly — silicon designing its successors.
The compression is the headline: design phases that consumed eighteen months of specialist effort now converge in weeks, with AI-generated layouts routinely beating hand-optimised baselines on power and density. Human architects have migrated up the stack, specifying constraints and adjudicating trade-offs rather than routing wires.
The strategic consequences ripple through the supply chain. Design-cycle speed becomes a competitive weapon as decisive as fabrication-node access, smaller firms can field credible custom silicon, and export-control regimes built around lithography confront a harder question: how to govern an input that is, increasingly, software teaching sand to think.